Sir
When a design engineer writes any Verilog code ,
his only aim is to get synthesis results as good as possible.
And in some cases it is not possible for him to modify the design just for the verification purpose, becoz synthesis results may become poorer.
In my previous mail you told me ,I cant use integer with
VIS(as these are not h/w implementable),but if its not possible for me to change the design, what I can do?
Thanking you
Vanessa
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