With vl2mv, integer variables cannot be used as you do in selectext,
because they are not translated into hardware.
Check http://vlsi.colorado.edu/~vis/doc/html/HowToWriteVerilogForVl2mv
for possible ways to solve your problem. In particular, the sections
on bit selection and parameterization.
Fabio
>>>>> "vg" == vanessa goyal <vanessa_goyal@rediffmail.com> writes:
vg> Sir
vg> For the following code,error coming is,
vg> "Variable J not declared while used as LHS".
vg> Please tell me What is the problem with the code?
vg> Thanking you
vg> Vanessa
vg> ******************************************
vg> module selectext (a, b,clk, out) ;
vg> input [3:0] a ;
vg> input [3:0] b ;
vg> input clk ;
vg> output [3:0] out ;
vg> reg [3:0] alatched ;
vg> reg [3:0] blatched ;
vg> reg [3:0] out ;
vg> integer j;
vg> always@ (posedge clk)
vg> begin
vg> alatched=a; blatched=b;
vg> end
vg> always@ (posedge clk)
vg> begin
vg> j=j+1;
vg> if(alatched[j]==1) out = blatched;
vg> else out= 0;
vg> end
vg> endmodule
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