Hello Sir
Functional simulation of following code,which is for 4x4 memory is working well over Xilinx fndtn. series but ,VIS is showing error .
For e.g. following property is failing.
AG((rwd=1 * file<*1*>[1:0]=3 * inxd=1)->AX(do[1:0]=3));
which should not fail.
Please tell me the reason of failure.
I observed the counterexample also,I am not getting why
the next state of
rwd=1
file<*1*>[1:0]=3
inxd=1
is,what counterexample is showing.
********************************************************
CODE USED FOR FUNCTIONAL SIMULATION OVER XILINX
******************************************************
module memory(clk,rw,inx,di,do);
//parameter n=2,m=2;
input clk,rw;
input inx;
input [1:0] di;
output [1:0] do;
//reg rwd;
//reg inxd;
//reg[1:0] did;
reg [1:0] do;
reg [1:0] file [1:0];
//initial begin
//file[0]=0;
//file[1]=0;
//do=0;
//end
//always @ (negedge clk)
//begin
//rwd=rw;inxd=inx;did=di;
//end
always @ (negedge clk)
if (rw) do=file[inx];
else file[inx]=di;
endmodule
*******************************************************
CODE USED WITH VIS
*******************************************************
module memory(clk,rw,inx,di,do);
//parameter n=2,m=2;
input clk,rw;
input inx;
input [1:0] di;
output [1:0] do;
reg rwd;
reg inxd;
reg[1:0] did;
reg [1:0] do;
reg [1:0] file [1:0];
initial begin
file[0]=0;
file[1]=0;
do=0;
end
always @ (negedge clk)
begin
rwd=rw;inxd=inx;did=di;
end
always @ (negedge clk)
if (rwd) do=file[inxd];
else file[inxd]=did;
endmodule
Thanking you
Vanessa
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