>
> If the FAQ does not help, please send us the verilog file, or preferably
> a very simple verilog file that exhibits the same problem, and we will
> have a look.
The problems I was facing, were becåuse I was using multiple
signals in the sensitivity list and because I was using non-blocking
assignments. I had corrected all that and was able to work with the
code. Thank you.
I am still facing a small problem with another piece of code. I had
written a two bit counter, which was accepted by vl2mv. I even ran it
on the vsim simulator and got the correct signal trace. When I tried
to check the states it was going through though, I got a very funny
state machine in which the state 01 (lower bit first) was not
accessible from any other state. Simulation from VIS gave me the wrong
trace. I have attached the code.
Vijay.
This archive was generated by hypermail 2b30 : Wed Jun 06 2001 - 04:10:29 MDT