Hi,
I was trying to do a verification of a TAP controller as an academic
excercise. I have been uable to and these are the errors I received at
different stages:
1. reset is being re-used as clk.
(It would not generate the blif) There was one process which was
triggered by identical behaviour of reset and clk. I removed reset
from the sensitivity list as a result.
2. Model uses delay. Does not know how to synthesize.
I removed all delays from the model.
3. clock is not defined as the output of a table in the model.
I did not know what to do about this, so tried
read_verilog -c -F TAP.v
which was the only way I could get it to read the file. Without the -F
option, it gave
"unknown construct .timers"
as an error.
Once it accepted, it would not do a flatten heirarchy, because
"table <number> is not deterministic"
And the output for that just streamed across the screen, listing a lot
of tables.
Please help.
Vijay D'silva.
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