about "eisenberg" in VIS

From: Guang Qu (g_qu@ece.concordia.ca)
Date: Wed May 23 2001 - 16:53:24 MDT

  • Next message: vanessa goyal: "fairness constraint"

    Hello,
    We are reading the example of "eisenberg" code for our project of the
    course-Formal Hardware Verification in Concordia University, but we do
    not understand what "$NDset(@(posedge clk), 0, 1)" and "$ND(0,1)" do.
    Are they new system tasks or functions in Verilog? Could you tell us
    where we can find the related information or give us some explanations
    about their functions (tasks?)?
    Thank you!

    Guang Qu

    This archive was generated by hypermail 2b30 : Wed May 23 2001 - 17:01:25 MDT