We are reading the example of "eisenberg" code for our project of the
course-Formal Hardware Verification in Concordia University, but we do
not understand what "$NDset(@(posedge clk), 0, 1)" and "$ND(0,1)" do.
Are they new system tasks or functions in Verilog? Could you tell us
where we can find the related information or give us some explanations
about their functions (tasks?)?
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