Re:

From: Roderick Bloem (roderick.bloem@colorado.edu)
Date: Tue May 22 2001 - 09:37:08 MDT

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    Hi Vanessa,

    You have to refer to the file as file<*1*>[1:0]. The number between <*
    and *> refers to the array index, and the [1:0] refers to the entire
    bitvector that file<*1*> is.

    I must admit the reference to arrays is rather obscure.

    Maybe you can help us by telling us how to improve the documentation...

    Best,

    Roderick

    vanessa goyal wrote:
    >
    > sir
    > In the following codes(first for programmable counter and second for memory)there is not much difference between
    > variables "counter"and "file".First code is working well but
    > second is giving error for property
    > AG((rwd=0)*(did[1:0]=3)*(inxd=1)->AX(file[1]=3));
    > "could not find node corresponding to the name file".
    > what mistake i am doing with variable file?
    > thanking you
    > vanessa
    > **********programmable counter*************************
    >
    > module bc(ck,p,c,u,q);
    > input ck,p,c,u;
    > output[2:0]q;
    > reg clatched,platched,ulatched;
    > reg[2:0]counter;
    > assign q = counter;
    > initial
    > begin
    > counter = 0;
    > clatched=0;platched=0;ulatched=0;
    > end
    > always @(posedge ck)
    > begin
    > clatched=c;platched=p;ulatched=u;
    > end
    > always @ (posedge ck)
    > if(clatched) counter=0;
    > else if(platched) counter=7;
    > else if(ulatched)counter=counter+1;
    > else counter= counter-1;
    > endmodule
    > ***************memory*************
    > module memory(clk,rw,inx,di,do);
    > //parameter n=2,m=2;
    > input clk,rw;
    > input inx;
    > input [1:0] di;
    > output [1:0] do;
    > reg rwd;
    > reg inxd;
    > reg[1:0] did;
    > reg [1:0] do;
    > reg [1:0] file [1:0];
    > initial begin
    > file[0]=0;
    > file[1]=0;
    > do=0;
    > end
    > always @ (negedge clk)
    > begin
    > rwd=rw;inxd=inx;did=di;
    > end
    > always @ (negedge clk)
    > if (rwd) do=file[inxd];
    > else file[inxd]=did;
    > endmodule
    >
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