> Respected sir,
> Thank you for your reply.But before your reply came,i was testing the .mv
> file on vis-1.2 version.To my surprise,it's not giving the error
> message as given by vis-1.3 version.I donot know whats the reason.I am now
> working on vis-1.2 only.Please tell me what might be the reason.I am using
> the vl2mv.linux executable file that is provided in the colorado VIS-FAQ.
> I am working on Linux platform.
>
>
> Thanking you sir,
> Prahallad.
>
>
> On Thu, 9 Nov 2000, Roderick Bloem wrote:
>
> > Prahallad,
> >
> > I think I have identofied where the problem comes from. I don't have a
> > solution, maybe someone else knows one?
> >
> > Your system has multiple drivers for the same signal. In particular,
> > the cache module has two always@(posedge clock) blocks, both of which
> > drive transReqPending. Although this may be legal Verilog (I cannot
> > judge that), vl2mv does not allow it.
> >
> > I can se two solutions:
> > * Rewrite the model to conform to vl2mv specifics.
> > * Use a synthesis tool to obtain the blif. (See the FAQ.)
> >
> > Maybe someone else knows whether there is an option to vl2mv to do
> > this? Has ST been seen recently?
> >
> > Below is a small model that exhibits the same problem.
> >
> > Roderick.
> >
> > prahallad wrote:
> > >
> > > Dear sir,
> > > I am M.Tech student in IITKanpur doing Microelectronics.As part of our m.Tech
> > > Thesis,I am working on the formal verification.
> > > I have installed VIS(ver 1.3) in Linux mandrake.I have got the vl2mv(linux
> > > version)executable from the VIS website.
> > > Vl2mv is converting the verilog file into corresponding .mv file.After that VIS
> > > is reading the .mv file by read-blif_mv command.But when i am doing init_verify
> > > it is giving the following errors.
> > > Is there problem in the verilog code?or vl2mv is creating problems?
> > > I am attaching the verilog file and BLIF-MV file(created through vl2mv).
> > >
> > > The error is as follows:
> > >
> > > vis> read_blif_mv ls_ls_v01.mv
> > > Warning: Some variables are unused in model PENTIUM_PRO_SYSTEM.
> > > Warning: Model P6 may have a cyclic connection which involves variable
> > > EXT_DATA_O<0>
> > > Warning: Some variables are unused in model MEMORY.
> > > Warning: Some variables are unused in model EU.
> > > Warning: Some variables are unused in model REQUEST_AGENT.
> > > vis> init_verify
> > > Table processor0.CACHE1._n181e is not deterministic
> > > Table processor0.CACHE1._n1841<0> is not deterministic
> > etc etc
>
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