---------- Forwarded message ----------
Date: Wed, 11 Oct 2000 11:16:55 +0530 (IST)
From: "K T Oommen Tharakan(99407703)" <tharakan@bhairav.ee.iitb.ernet.in>
To: vis@ic.eecs.berkeley.edu
Subject: Usage of VIS
Dear Sirs:
I am a PH.D scholar in the Department of Electrical Engg. at Indian
Institute of Technology, Bombay, India. My area of research is in Formal
Verification.
In the process of ambling different tools I came across VIS. I would like
to know the following on VIS.
1. Whether VIS accepts VHDL codes or is it currently restricted to Verilog
only?
2. If not, whether there is any tool to convert from VHDL to BLIF format
or VHDL to Verilog. Kindly let me know.
Looking forward to your reply,
With best regards,
K T Oommen Tharakan
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K T Oommen Tharakan
Research Scholar
Room No: 72, Hostel No: 1 [QUEEN]
Indian Institute of Technology-Bombay
Powai, Mumbai, INDIA
PIN: 400 076
Email id: tharakan@ee.iitb.ernet.in
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