My earlier question was regarding how to translate Verilog into BLIF using
vl2mv. You mentioned that Synopsys is an alternative to vl2mv. Well, we do
have the Synopsys tools, so what should I do? I just need my designs in
BLIF, because I need to use another tool (flowmap from UCLA) which takes
BLIF as input.
Right now, I'm considering using Synopsys to convert Verilog to gate
netlist, and then write a translator from the netlist to BLIF. It seems like
it would be straightfoward. Has anybody done that?
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