Rainer,
There's no real alternative to using vl2mv, unless you have a commercial
design compiler such as Synopsys or Altera.
Swapping two resisters can be done like this:
module n(clk);
input clk;
reg a,b;
wire c;
assign c = a;
initial begin a=0; b=1; end
always @(clk) begin
a = b;
b = c;
end
endmodule
Don't know whether this conforms to verilog semantics, but it works in
vl2mv.
Roderick.
Rainer Dorsch wrote:
>
> Roderick,
>
> thanks for your reply and fixing the code. Someone pointed out that the -q option should fix the behavior.
>
> >
> > Yes. Vl2mv is a mess.
> >
>
> I am not bound on Verilog. Is there a better way to generate the BLIF-MV files than Veriolog-vl2mv for the model description?
>
> > No, no , and no.
> Hmm, how would you swap the content of two registers like
>
> always(..) begin
> a<=b;
> b<=a;
> end
>
> ?
>
> Thanks.
>
> Rainer.
>
> _______________________________________________________________________
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