work-around for non-blocking assignments

From: Tim Tuan (timt@bwrc.eecs.berkeley.edu)
Date: Wed Aug 02 2000 - 17:05:21 MDT

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    Hi,

    I'm attempting to use VIS to translate a bunch of Verilog code to BLIF.
    However, my code uses non-blocking assignments (<=) extensively, which is
    not supported by VIS. Have anyone experienced the same deficiency? Are there
    any good work-arounds?

    Thanks,
    Tim

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