Re: simulate problem

From: Rainer Dorsch (rdorsch@web.de)
Date: Wed Aug 02 2000 - 10:00:17 MDT

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    Roderick,

    thanks for your reply and fixing the code. Someone pointed out that the -q option should fix the behavior.

    >
    > Yes. Vl2mv is a mess.
    >

    I am not bound on Verilog. Is there a better way to generate the BLIF-MV files than Veriolog-vl2mv for the model description?

    > No, no , and no.
    Hmm, how would you swap the content of two registers like

    always(..) begin
      a<=b;
      b<=a;
    end

    ?

    Thanks.

    Rainer.

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