Hi Rainer,
I am not sure what exactly your question is, but it aqppears that the
bit order in the {,} operator is the opposite of what you would expect.
Thus, in your example, creg[0] is the LSB, but it mysteriously appears
to the right in the {,} operator.
Let's wait and see what Fabio says when he comes in.
Roderick.
PS: Something seems to be wrong with your .forward or .vacation. I get
strange mail back.
Rainer Dorsch wrote:
>
> Thanks for the immediate reply. It worked for the example. But I am still somewhat confused about the bit ordering. The code from Fabio Somenzi in rcnum.v looks reasonable:
>
> // Compute n[i] * 3 + 1.
> assign tmp = {2'b0,numOut} + {1'b0,numOut,1'b1};
>
> tmp is declared as " wire [24+2:0] tmp; " and it seems that the MSB is rightmost.
>
> In my own example, it seems that shifting to the left (MSB bit seems to be rightmost) works only if done as
>
> creg = {in,creg[WIDTH-2:0]};
>
> and creg is also defined as " reg[WIDTH-1:0] creg;"
>
> The complete code:
> module accu(clk, in, out);
> parameter WIDTH = 5;
> input clk, in;
> output[WIDTH-1:0] out;
> reg[WIDTH-1:0] acc;
> reg[WIDTH-1:0] creg;
>
> assign out = acc[WIDTH-1:0];
>
> initial acc = 2;
> initial creg = 3;
>
> always @(posedge clk) begin
> acc = acc + creg;
> creg = {in,creg[WIDTH-2:0]}; // LSB seems to be left (from simulate -n10)
> end
>
> endmodule
>
> The simulation output:
> vis> simulate -n 6
> # vis release 1.3 (compiled 31-Jul-00 at 11:49 PM)
> # Network: accu
> # Simulation vectors have been randomly generated
>
> ..inputs in
> ..latches acc<0> acc<1> acc<2> acc<3> acc<4> creg<0> creg<1> creg<2> creg<3> creg<4>
> ..outputs out<0> out<1> out<2> out<3> out<4>
> ..initial 0 1 0 0 0 1 1 0 0 0
>
> ..start_vectors
>
> # in ; acc<0> acc<1> acc<2> acc<3> acc<4> creg<0> creg<1> creg<2> creg<3> creg<4> ; out<0> out<1> out<2> out<3> out<4>
>
> 0 ; 0 1 0 0 0 1 1 0 0 0 ; 0 1 0 0 0
> 0 ; 1 0 1 0 0 0 1 1 0 0 ; 1 0 1 0 0
> 0 ; 1 1 0 1 0 0 0 1 1 0 ; 1 1 0 1 0
> 1 ; 1 1 1 0 1 0 0 0 1 1 ; 1 1 1 0 1
> 1 ; 1 1 1 1 0 1 0 0 0 1 ; 1 1 1 1 0
> 0 ; 0 0 0 0 0 1 1 0 0 0 ; 0 0 0 0 0
> # Final State : 0 0 0 0 0 1 1 0 0 0
> vis>
>
> Does anybody know, where the difference from Fabio's code (which seems to be right) and my own code (which is experimentally derived and seems to work) comes from?
>
> Thanks.
>
> Rainer.
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