Thanks for the immediate reply. It worked for the example. But I am still somewhat confused about the bit ordering. The code from Fabio Somenzi in rcnum.v looks reasonable:
// Compute n[i] * 3 + 1.
assign tmp = {2'b0,numOut} + {1'b0,numOut,1'b1};
tmp is declared as " wire [24+2:0] tmp; " and it seems that the MSB is rightmost.
In my own example, it seems that shifting to the left (MSB bit seems to be rightmost) works only if done as
creg = {in,creg[WIDTH-2:0]};
and creg is also defined as " reg[WIDTH-1:0] creg;"
The complete code:
module accu(clk, in, out);
parameter WIDTH = 5;
input clk, in;
output[WIDTH-1:0] out;
reg[WIDTH-1:0] acc;
reg[WIDTH-1:0] creg;
assign out = acc[WIDTH-1:0];
initial acc = 2;
initial creg = 3;
always @(posedge clk) begin
acc = acc + creg;
creg = {in,creg[WIDTH-2:0]}; // LSB seems to be left (from simulate -n10)
end
endmodule
The simulation output:
vis> simulate -n 6
# vis release 1.3 (compiled 31-Jul-00 at 11:49 PM)
# Network: accu
# Simulation vectors have been randomly generated
..inputs in
..latches acc<0> acc<1> acc<2> acc<3> acc<4> creg<0> creg<1> creg<2> creg<3> creg<4>
..outputs out<0> out<1> out<2> out<3> out<4>
..initial 0 1 0 0 0 1 1 0 0 0
..start_vectors
# in ; acc<0> acc<1> acc<2> acc<3> acc<4> creg<0> creg<1> creg<2> creg<3> creg<4> ; out<0> out<1> out<2> out<3> out<4>
0 ; 0 1 0 0 0 1 1 0 0 0 ; 0 1 0 0 0
0 ; 1 0 1 0 0 0 1 1 0 0 ; 1 0 1 0 0
0 ; 1 1 0 1 0 0 0 1 1 0 ; 1 1 0 1 0
1 ; 1 1 1 0 1 0 0 0 1 1 ; 1 1 1 0 1
1 ; 1 1 1 1 0 1 0 0 0 1 ; 1 1 1 1 0
0 ; 0 0 0 0 0 1 1 0 0 0 ; 0 0 0 0 0
# Final State : 0 0 0 0 0 1 1 0 0 0
vis>
Does anybody know, where the difference from Fabio's code (which seems to be right) and my own code (which is experimentally derived and seems to work) comes from?
Thanks.
Rainer.
vis-users@lists.Colorado.EDU schrieb am 02.08.00:
> use: vl2mv -q <file>.v
>
> -malay
> --- Rainer Dorsch
> <rainer@rai16.informatik.uni-stuttgart.de> wrote:
> >
> > Hello,
> >
> > I am experimenting with VIS and Verilog. Since I
> > knew none of both
> > before, I am wondering, if anybody can give me a
> > hint what could be
> > wrong in the following example:
> >
> > module accu(clk, in, out);
> > parameter WIDTH = 5; // size of significand minus
> > hidden bit
> > parameter QUEUE = 1; //
> > input clk, in;
> > output[0:(QUEUE*WIDTH)-1] out;
> > reg[0:(QUEUE*WIDTH)-1] acc, creg;
> >
> > assign out = acc;
> >
> > initial acc = 2;
> > initial creg = 2;
> >
> > always @(posedge clk) begin
> > acc = acc + creg;
> > creg = {in,creg[0:WIDTH-2]}; // LSB seems to be
> > left (from simulate -n10)
> > end
> >
> > endmodule
> >
> > First I expect output to be the same as acc and I
> > would expect that
> > acc in the second cycle is 4.
> >
> > I convert it to blif_mv using vl2mv then I read it
> > using
> > read_blif_mf. After init_verify, I simulate the
> > circuit and I obtain
> >
> > vis> simulate -n 2
> > # vis release 1.3 (compiled 31-Jul-00 at 11:49 PM)
> > # Network: accu
> > # Simulation vectors have been randomly generated
> >
> >
> > .inputs in
> > .latches acc<0> acc<1> acc<2> acc<3> acc<4> creg<0>
> > creg<1> creg<2> creg<3> creg<4>
> > .outputs out<0> out<1> out<2> out<3> out<4>
> > .initial 0 0 0 1 0 0 0 0 1 0
> >
> > .start_vectors
> >
> > # in ; acc<0> acc<1> acc<2> acc<3> acc<4> creg<0>
> > creg<1> creg<2> creg<3> creg<4> ; out<0> out<1>
> > out<2> out<3> out<4>
> >
> > 0 ; 0 0 0 1 0 0 0 0 1 0 ; 0 1 0 0 0
> > 1 ; 1 0 0 0 0 0 0 0 1 0 ; 0 0 0 0 1
> > # Final State : 1 0 0 0 0 0 0 0 1 0
> > vis>
> >
> >
> > No matter how I interpret the acc in cycle 2, it is
> > either 1 or 16.
> >
> > Is there a problem with vl2mv (the .mv file is
> > available at
> >
> http://www.ra.informatik.uni-stuttgart.de/~rainer/Download/demo.mv
> > for
> > inspection)?
> >
> > Or is simply the simulate command in vis not
> > working?
> >
> > Or is there simply something terribly wrong with my
> > verilog code?
> >
> >
> > Can vl2mv handle non-blocking assignments?
> >
> > Thank you.
> >
> > --
> > Rainer Dorsch
> > Abt. Rechnerarchitektur
> > e-mail:rainer.dorsch@informatik.uni-stuttgart.de
> > Uni Stuttgart Tel.: +49-711-7816-215 /
> > Fax: +49-711-7816-288
> > Breitwiesenstr. 20-22 D-70565 Stuttgart
>
>
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