Rainer,
The problem is with the bit order. Vl2mv can't handle bits that are
ordered 0..n, and you should order them n..0. Below is the changed code
that works with vl2mv.
> Is there a problem with vl2mv (the .mv file is available at
> http://www.ra.informatik.uni-stuttgart.de/~rainer/Download/demo.mv for
> inspection)?
Yes. Vl2mv is a mess.
> Or is simply the simulate command in vis not working?
> Or is there simply something terribly wrong with my verilog code?
> Can vl2mv handle non-blocking assignments?
No, no , and no.
Let us know if you have more problems, we'll be glad to help out more.
Best,
Roderick.
module accu(clk, in, out);
parameter WIDTH = 5; // size of significand minus hidden bit
parameter QUEUE = 1; //
input clk, in;
output[(QUEUE*WIDTH)-1:0] out;
reg[(QUEUE*WIDTH)-1:0] acc, creg;
assign out = acc;
initial acc = 2;
initial creg = 2;
always @(posedge clk) begin
acc = acc + creg;
creg = {in,creg[WIDTH-2:0]}; // LSB seems to be left (from simulate
-n10)
end
endmodule
This archive was generated by hypermail 2b29 : Wed Aug 02 2000 - 02:24:13 MDT