VIS Pl. help

From: P.K. Pandya (pandya@tcs.tifr.res.in)
Date: Fri Jul 14 2000 - 04:31:31 MDT

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Dear VIS group members,

I am a new user of VIS. Can you pl. help with the following issues?

1. Sometimes variables used in original Verilog file are no longer
visible to the CTL formula during
model_check.
Is there any workaround? Will it help if they are declared as
output?

2. The debugger of model_check command does not show all the (output)
variables.
Is there any way we can direct it to show required information?

Can the error trace generated by debugger be given to simulate
command?

Thanks for your help in advance.

with best regards
Paritosh Pandya

--
Paritosh K. Pandya,  Computer Science Group, Tata Institute of
Fundamental Research, Homi Bhabha Road, Colaba, Mumbai 400 005 India
Ph.  +91-22-2188725   Email: pandya@tcs.tifr.res.in
http://www.tcs.tifr.res.in/~pandya

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