attached mail follows:
Is the construct like above not supported my vis. If not can you tell me
how can i use a memory of say 15 bytes which i want to index using
variable.
I am attaching both the verilog file.
Thanking you,
bye,
uday.
--azLHFNyN32YCQGCU
Content-Type: text/plain; charset=us-ascii
Content-Disposition: attachment; filename="exeunit.v"
`define CONTROL_SZ 5
`define ADDR_SIZE 3:0
`define DATA_SIZE 3:0
`define BURST_DATA_SIZE 15:0
`define CONTROL_SIZE `CONTROL_SZ:0
typedef enum {TI,TR,TO,TO1,TE} Statpro;
typedef enum {TQ,TS,TAD,TA,TE} Statque;
typedef enum {TI,TA,TD,TO,TO1,TAD} Statexe;
typedef enum {TA,TD,TI,TR,TW} Statbus;
module exec_unit(go,clk,addressin,datain,data1in,dataout,isburst,controlin,
byteenable,ladout,ready,request,read,outputl,outputs,shift);
input go,clk,addressin,datain,ready,data1in,controlin;
output dataout,isburst,request,ladout,read,outputl,outputs;
output byteenable,shift;
wire clk,go,ready;
wire [`ADDR_SIZE] addressin;
wire [`BURST_DATA_SIZE] datain;
wire [`DATA_SIZE] data1in;
wire [`CONTROL_SIZE] controlin;
reg isburst,request,outputl,outputs,shift;
reg [`DATA_SIZE] byteen,byteenable;
reg [`ADDR_SIZE] ladout;
reg [`BURST_DATA_SIZE] dataout;
reg [`ADDR_SIZE] qaddress;
reg [`CONTROL_SZ-1:0] no_bytes;
reg [`DATA_SIZE] prev;
reg [`CONTROL_SIZE] qcontrol;
reg qdata[`BURST_DATA_SIZE];
reg [2:0] this_trans;
reg read;
reg times;
reg [4:0] no_bytes,bytes;
initial times=0;
initial shift=0;
initial read=0;
initial byteen=0;
initial byteenable=0;
initial no_bytes=0;
initial dataout=0;
initial ladout=0;
initial bytes=0;
initial this_trans=0;
initial outputs=0;
initial outputl=0;
initial isburst=0;
initial qcontrol=0;
initial request=0;
initial qaddress=0;
initial qdata=0;
Statexe reg States;
initial States=TI;
initial prev=0;
always @(posedge clk)
begin
case(States)
TI:
if(go==1)
begin
qaddress=addressin;
outputl=0;
outputs=0;
/* qdata=datain;*/
read=qcontrol[0];
no_bytes=qcontrol[`CONTROL_SZ:1];
request=1;
States=TA;
end
TA:
begin
ladout=qaddress;
States=TD;
if((no_bytes - (4 - qaddress[1:0] )) >0)
isburst=1;
else
isburst=0;
if((no_bytes - (4 - qaddress[1:0])) < 0)
begin
this_trans=no_bytes;
no_bytes=0;
end
else
begin
no_bytes = no_bytes - ( 4 -qaddress[1:0]);
this_trans = 4 - qaddress[1:0];
end
case(this_trans)
1:
case(qaddress[1:0])
0: byteen = 4'b0001;
1: byteen = 4'b0010;
2: byteen = 4'b0100;
3: byteen = 4'b1000;
endcase
2:
case(qaddress[1:0])
0: byteen = 4'b0011;
1: byteen = 4'b0110;
2: byteen = 4'b1100;
endcase
3:
case(qaddress[1:0])
0: byteen = 4'b0111;
1: byteen = 4'b1110;
endcase
4:
byteen = 4'b1111;
endcase
if(read==0)
byteenable=byteen;
end
TD:
begin
if(ready==1)
if(no_bytes > 4)
begin
States=TD;
isburst=1;
end
else
begin
if(read==0)begin
States=TO1;
outputl=1;
end
else begin outputs=1; States=TO;end
isburst=0;
end
if(no_bytes >4) begin this_trans=4 ;no_bytes=no_bytes-4;end
else begin this_trans=no_bytes;no_bytes=0;end
prev=byteen;
case(this_trans)
1: byteen = 4'b0001;
2: byteen = 4'b0011;
3: byteen = 4'b0111;
4: byteen = 4'b1111;
endcase
if(read==0)
begin
byteenable=byteen;
//ladout=qdata[3:0];
end
else
case(prev)
4'b0001: begin
//qdata[bytes]=data1in[0];
bytes=bytes+1;end
4'b0011: begin
/* qdata[bytes]=data1in[0];
qdata[bytes+1]=data1in[1];*/
bytes=bytes+2;
end
4'b0111:begin
/*qdata[bytes]=data1in[0];
qdata[bytes+1]=data1in[1];
qdata[bytes+2]=data1in[2];*/
bytes=bytes+3;
end
4'b1111:begin
/*qdata[bytes]=data1in[0];
qdata[bytes+1]=data1in[1];
qdata[bytes+2]=data1in[2];
qdata[bytes+3]=data1in[3];*/
end
endcase
end
TO:begin
outputs=0;
shift=1;
States=TI;end
TO1:begin
outputl=0;
States=TAD;
/* dataout=qdata; */
end
TAD: begin shift=1;States=TI;end
endcase
end
endmodule
--azLHFNyN32YCQGCU--
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