Synthesis in VIS

VIS can interact with SIS in order to optimize the existing logic. There are two possible goals/scenarios:

1.

Synthesis for verification : Synthesis can be used to optimize the logic that represents the system, for simpler verification.

2.

Front-end to synthesis : Files described in Verilog and compiled into blif_mv (using VL2MV or another tool) can be synthesized by using VIS and SIS together.

A key fact is that only the current level of the hierarchy is sent to SIS, and not the subtree rooted at the current node. ^* Modules at a lower level are treated as external and the boundary variables are carefully preserved, by reintegrating their multi-valued status after the optimization step in SIS (SIS requires that boundary variables are completely encoded, i.e., are binary variables).

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* One would need a flattening routine different form the one which starts the verification
flow already in VIS, and such a routine to flatten for sysnthesis is not yet available.