My research interest is focussed in the following areas:

[A-Z]DD: Decision Diagrams applied to synthesis and verification of digital systems

Formal Verification of Digital Systems.


I graduated from the University of Colorado at Boulder in the summer of 1997. You may access my Ph. D. Thesis.
I am a member of the team that is developing VIS, an interactive system for verification and synthesis. For more information, software download, trial run and much more take a look at the VIS Home Page
VLSI Group Seminar.(For VLSI/CAD members only)
Anecdotes about the use of Formal Methods
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